A 10 Bit 40-MS/s Pipelined Analog-to-Digital Converter for IEEE 802.11a WLAN Systems

This work describes a 10-bit 40MS/s pipelined analog-to-digital converter (ADC) which is used in IEEE 802.11a WLAN system. This pipelined ADC is consisted of one sample-and-hold (S/H) circuit and nine uniform pipelined stages. In this pipelined ADC, the resolution for the S/H circuit and each single pipelined stage is up to 12 bit and 14 bit respectively at 8 MHz input frequency. The spurious free dynamic range (SFDR) of S/H and each single pipelined stage are up to 91 dBc and 120 dBc respectively. These high performances meet the requirement of IEEE 802.11a standard with the 8MHz bandwidth and the 10-bit resolution.